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XBEGIN

Starts a transactional memory block. The instruction saves the current state of the processor and checkpoints the register state. If a transaction is already in progress, XBEGIN is ignored. If a transaction fails, the processor rolls back the architectural state to the checkpoint created by XBEGIN and transfers control to the fallback address specified by the operand.

The following table covers what the source and destinations can be:

DO NOT support LOCK

XBEGIN is only available in 64-bit mode. It is NOT supported in compatibility mode. The instruction requires the processor to support Intel TSX (Transactional Synchronization Extensions).

The fallback address provided as an immediate or register must be a valid memory address within the current execution context to avoid a General Protection fault (#GP) upon transaction abort. If the RTM (Restrictive Transactional Memory) feature is disabled in CR4.RTM, executing XBEGIN SHALL trigger an invalid opcode exception (#UD).