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VSUBPH

Subtracts two packed half-precision floating-point values.

The following table covers the supported source and destination operands.

DO NOT support LOCK

This instruction is only available when the processor supports the AVX-512 FP16 extension. It operates on registers in 64-bit mode or compatibility mode.

The destination register is overwritten by the result; therefore, if the destination is also a source, the original value is lost. When using the memory operand, the alignment of the memory region SHALL be compatible with the vector size to avoid performance penalties or faults depending on the alignment check settings.