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VSQRTPH

Computes the square root of the lower 16 bits of the source operand as a half-precision floating-point number and stores the result in the destination operand.

The table below covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires the AVX-512 FP16 extension.

The instruction supports rounding control via the round-control field in the EVEX prefix; if the field is set to 00, the rounding is governed by the MXCSR register. If the input is a NaN, the result is a qNaN. If the input is negative, the instruction generates #I and returns a qNaN. If the input is zero, the result is zero with the sign of the input. Precision #P is raised if the result is not exact.