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VSCATTERPF1QPS

VSCATTERPF1QPS scatters packed single-precision floating-point values from a ZMM register to memory locations specified by an index vector. For each single-precision value, the instruction calculates the destination address by adding the index (scaled by the size of a single-precision float) to a base address. It then stores the value at that address.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is available only when the processor supports AVX-512. It requires the AVX-512 foundation (AVX512F) and the AVX-512 Conflict Detection Instruction Set (AVX512CD) if specific conflict-avoidance logic is utilized, though the basic scatter operation is part of AVX512F. It operates in 64-bit mode.

To avoid incorrect memory operations, the user SHALL ensure that the index vector does not contain values that cause the calculated address to exceed the architectural address limit. Since this instruction performs multiple memory writes, it does not guarantee atomicity across the entire vector; each element is stored independently. If multiple indices point to the same memory location, the final value stored is determined by the order of execution, which is generally sequential relative to the element index.