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VSCATTERPF1DPS

Stores a single-precision floating-point value from a zmm register to a memory location based on an index from another zmm register, applying a mask.

The following table specifies the supported sources and destinations.

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires AVX-512 support (specifically AVX-512PF).

The index register must contain signed 32-bit integers. If the mask bit is 0, the store operation for that specific element SHALL NOT be performed. Memory accesses MUST be aligned to the requirements of the data type to avoid performance degradation, although the instruction supports unaligned accesses. Multiple indices pointing to the same memory address result in undefined behavior regarding the final value stored.