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VSCATTERPF1DPD

VSCATTERPF1DPD scatters double-precision floating-point values from a zmm register to memory locations based on indices provided by another zmm register. For each active element indicated by the mask, the instruction writes a 64-bit floating-point value to the address calculated by adding the scaled index to the base address.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction SHALL only be executed in 64-bit mode. It is not supported in compatibility mode.

The instruction requires the AVX-512 foundation and the AVX-512PF (Prefetch) extension. If the processor does not support AVX-512PF, executing this instruction SHALL trigger an invalid opcode exception.

The behavior of VSCATTERPF1DPD is non-deterministic regarding the order of memory writes. If multiple indices point to the same memory location, the final value written is not guaranteed. Users MUST ensure that the index register does not contain overlapping addresses if the sequence of writes is critical to the application logic. Masking SHALL be used to prevent invalid memory accesses; any element with a mask bit set to 0 is ignored and no memory operation is performed for that index.