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VSCATTERPF0DPD

This instruction stores packed double-precision floating-point values from a zmm register to memory locations specified by an index vector. It uses the provided base address and a scale factor to calculate the effective addresses for each element.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires AVX-512 support (specifically AVX-512F) to be enabled.

The instruction utilizes a mask register to determine which elements are stored; elements with a mask bit set to 0 are not written to memory. When the mask is not used, all elements are processed. Since this instruction performs multiple memory writes, it is subject to memory aliasing; if multiple indices point to the same memory location, the final value stored is determined by the order of the elements in the vector. To avoid undefined behavior or data corruption in multi-threaded environments, software MUST ensure proper synchronization or use unique indices.