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VPTESTNMQ

Performs a bitwise logical AND operation between two 512-bit YMM/ZMM registers or a register and a memory operand, and sets the flags based on the result. If the result of the AND operation is non-zero, the Zero Flag (ZF) is cleared; otherwise, it is set.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires the AVX-512 foundation extensions to be enabled.

The instruction updates the RFLAGS register; specifically, it modifies the ZF flag. Users MUST ensure that the target memory operand is aligned to 64 bytes to avoid potential performance penalties or general protection faults depending on the alignment check settings.