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VPTESTNMD

Performs a logical AND operation between the first source operand and the second source operand, then tests the result against zero. If the result of the AND operation is non-zero, the Carry Flag (CF) is cleared; otherwise, the Carry Flag (CF) is set. The Zero Flag (ZF) is updated based on the result of the operation.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is only available in 64-bit mode. In compatibility mode, attempting to execute this instruction will result in an invalid opcode exception.

The instruction uses the mask register (k-register) if the EVEX prefix is present to control which elements of the vector registers are processed. If a mask is used and the mask bit for a specific element is 0, the corresponding element in the source operands is not accessed, and the result for that element does not affect the flags. Ensure that the appropriate mask register is initialized to avoid unexpected behavior in the conditional flags.