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VPTESTNMB

Performs a bitwise logical AND operation between two mask registers and sets the ZF flag in the FLAGS register based on the result. If the result of the logical AND is non-zero, ZF is cleared; if the result is zero, ZF is set.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is only available in 64-bit mode. It requires the AVX-512 foundation.

The destination operand is an implicit destination as the instruction only modifies the flags register. Users SHALL ensure that the mask registers used are valid and within the supported bit-width of the architecture to avoid undefined behavior. Failure to target a 64-bit environment WILL result in an illegal instruction exception.