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VPTESTMQ

Performs a bitwise logical AND between two qword-sized elements of the source operands. If the result of the AND operation is non-zero, the corresponding bit in the destination register is set to 1; otherwise, it is set to 0.

The table below covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires the AVX-512 foundation.

The instruction updates the mask register kx. If the destination mask register is specified as a general-purpose register, the result is written to the lower bits of that register. Ensure the target mask register is correctly sized to avoid unintended data loss or incorrect conditional branching.