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VPTERNLOGD

Computes a bitwise logical operation on three 32-bit packed doubleword vector operands. The specific operation is selected by an 8-bit immediate value, which acts as a truth table for the three inputs. The result is stored in the destination operand.

The table below covers what the source and destinations can be.

DO NOT support LOCK

This instruction is ONLY available in 64-bit mode or compatibility mode. It requires the AVX-512 foundation (AVX512F) to be supported by the processor.

When using the instruction with a memory operand, it SHALL be naturally aligned to the size of the vector register used to avoid potential performance penalties or alignment faults. If masking is applied (K-mask), the behavior regarding the destination register depends on the mask bit; if the bit is 0, the destination element is either zeroed or preserved based on the masking type (merging-masking vs zeroing-masking). Failure to specify the correct mask register for the operand width MAY result in undefined behavior.