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VPSRLVQ

Shifts the unsigned 64-bit integers in the destination vector by the number of bits specified in the source vector. The shift count is taken from the low 6 bits of the source element, and the result is stored in the destination vector.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

This instruction requires AVX-512 support. It is only available in 64-bit mode.

The shift count is masked to 6 bits (0-63); any bits beyond the 6th bit in the source register/memory operand are ignored. Failure to ensure the shift count is within the 0-63 range may lead to unexpected behavior if the programmer assumes a larger shift is possible. This instruction operates on zmm registers; using it with smaller vector registers (ymm/xmm) is not supported by this specific mnemonic.