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VPSRLVD

Shifts the unsigned doublewords in the destination vector right by the number of bits specified by the corresponding doubleword in the source vector. The result is stored in the destination vector.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode. If executed in compatibility mode, it will trigger an invalid opcode exception.

The shift count is masked to 31 bits; any bits beyond the 5th bit of the shift count are ignored. If the shift count is greater than or equal to 32, the result is zero. Ensure that the input vector is correctly aligned to the corresponding vector length to avoid general protection faults.