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VPSRAVW

Shift right arithmetic each 32-bit element of a packed 256-bit vector by the count specified in the immediate or the source register. The sign bit of each 32-bit element is replicated into the most significant bits.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires the AVX2 instruction set extension to be supported by the processor.

The shift count is masked to 5 bits (0-31) for 32-bit elements; any bits beyond the 5th bit in the immediate or register are ignored. Failure to mask the shift count manually before execution may result in unintended shift amounts if the value exceeds 31.