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VPSRAVD

Shifts the signed doubleword elements in the source operand to the right by the count specified by the second source operand. The sign bit is replicated to fill the vacated leftmost positions of each element. The result is stored in the destination operand.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires the AVX CPU feature to be enabled.

The shift count is masked to 5 bits (0-31). If the shift count is greater than or equal to 32, the result for those elements is defined as zero, except for the sign bit which is preserved based on the original value's sign. Use of this instruction in 32-bit mode is prohibited.