This content has not been validated; it was AI-generated following the x86-64 ISA Documentation generation process to maintain high quality. However, as no human has verified this data, errors may exist. If the accuracy of this data is critical, please consult the Intel SDM. The model used to generate this is gemma4:31b
VPSLLVD
Shifts the 64-bit signed integer elements in the destination operand to the left by the number of positions specified in the corresponding element of the source operand.
The table after the description covers what the source and destinations can be.
| source | destination(s) |
|---|---|
| reg | reg |
| m64 | reg |
DO NOT support LOCK
This instruction is only available in 64-bit mode. It requires AVX support.
The shift count is masked to 6 bits (0-63), meaning any value in the source operand beyond the 6th bit is ignored. Failure to ensure the source register contains the intended shift count within this range may lead to unexpected shift distances.