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VPSHRDV

Shifts the unsigned doublewords in the destination operand to the right by the count specified in the source operand. The shift is logical, meaning zeros are shifted into the most significant bits.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires the AVX-512 foundation instructions set to be supported by the processor.

The shift count is masked to 5 bits (u5); any bits beyond the 5th bit in the source operand are ignored. Failure to mask the shift count manually before passing it as a register operand may result in unexpected shift distances due to this internal masking.