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VPSHLDV

Shifts the doublewords in each packed 128-bit element of the first source operand to the left by the count specified in the second source operand. The shifted-out bits are filled with zeros, and the shift count is masked to u5.

The table below covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires AVX-512DQ support.

The shift count is masked to u5, meaning only the low-order 5 bits of the count operand are used; any bits beyond bit 4 are ignored. Failure to mask the count manually before execution is unnecessary but failure to account for this masking in logic may lead to unexpected shift distances.