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VPSHLD
Shifts the elements of a packed YMM or ZMM register to the left by a count specified by another register, filling the vacated bits with zeros.
The table after the description covers what the source and destinations can be.
| source | destination(s) |
|---|---|
| reg | reg |
| #I | mN |
DO NOT support LOCK
This instruction SHALL be used only in 64-bit mode or compatibility mode. It requires AVX-512 support (specifically AVX-512F) to be enabled in the processor.
The shift count is taken from the low-order bits of the source register; for a 32-bit element, only the bits 0-31 are used. If the shift count is greater than or equal to the element size, the result SHALL be zero. Using a memory operand for the destination is NOT supported.