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VPSCATTERQD

VPSCATTERQD scatters 64-bit quadword elements from a zmm register to memory locations specified by a vector of 64-bit indices. For each active element in the mask, the instruction calculates the destination address by adding the scaled index to a base address and stores the corresponding quadword from the source register.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction requires AVX-512 foundation support. It SHALL only operate in 64-bit mode or compatibility mode.

Masking is REQUIRED for this instruction; if the mask bit for an element is 0, the corresponding memory location is not accessed. This prevents unnecessary memory faults.

The instruction DOES NOT guarantee the order of stores; multiple indices pointing to the same memory address SHALL result in undefined behavior regarding which element is stored last. To ensure deterministic behavior when duplicate indices are present, the software MUST handle collisions manually. Memory disambiguation and potential alignment issues may affect performance, as the operation performs multiple non-contiguous stores.