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VPMOVSQW

Moves with sign-extension quadwords to words. Each 64-bit signed integer element from the source is sign-extended and truncated to a 16-bit signed integer element in the destination.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is available only in 64-bit mode. It requires the AVX-512BW instruction set extension to be supported by the processor.

To avoid undefined behavior or general protection faults, the destination register MUST be the same size as the source register if using the EVEX prefix to ensure consistent element processing. When using memory operands, the memory region MUST be aligned to the element size to prevent performance degradation or alignment checks.