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VPMOVQW

Zero-extends 16-bit signed integers from a source to 64-bit signed integers in a destination.

The following table specifies the supported source and destination operands.

DO NOT support LOCK

This instruction requires a processor with AVX-512 BW extensions. It is not available in compatibility mode for 32-bit applications if the AVX-512 BW feature is not explicitly supported by the operating system and hardware.

When using the EVEX encoding, the instruction supports masking. If a mask is applied, the merge or zeroing behavior is determined by the mask register; elements not enabled by the mask will either retain their original value or be zeroed, depending on the masking setting. Failure to account for mask behavior can result in corrupted destination data.