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VPMOVQ2M

Moves a quadword from a General Purpose Register (GPR) to a specified element of a packed 64-bit integer vector in a YMM or ZMM register.

The following table covers the supported source and destinations:

DO NOT support LOCK

This instruction is only available when the processor supports AVX-512 and is executing in 64-bit mode. It is not available in compatibility mode.

The destination register MUST be a YMM or ZMM register; using an XMM register will result in an invalid opcode. The specific element index within the destination vector is determined by the immediate operand, which MUST be within the range of the destination register's width. Failure to provide a valid immediate index will result in an encoding error.