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VPLZCNTQ

Counts the number of leading zeros in a quadword element of a SIMD register. If the input is zero, the result is the operand size (64).

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction SHALL be used only in 64-bit mode or compatibility mode. It requires the AVX-512 Foundation (AVX512F) instruction set extensions to be enabled.

The instruction's behavior is dependent on the LZCNT feature flag. If the processor does not support LZCNT, this instruction MAY result in an #I (Invalid Operation) or exhibit undefined behavior. When executing in a context where the LZCNT bit is not set in the CPUID, the instruction MUST NOT be used. Ensure that the target hardware supports AVX-512F to avoid illegal instruction exceptions.