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VPCMPW

Compares two word-sized signed integers in the source operands based on a specified immediate condition and stores the result in the destination operand. The comparison is performed element-wise across the vector registers.

The table below covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available in 64-bit mode and 32-bit mode. It REQUIRES the AVX-512BW instruction set extension.

The destination register MUST NOT be the same as the memory operand source to avoid undefined behavior in certain microarchitectures. Users SHOULD ensure that the immediate byte is a valid comparison predicate defined by the AVX-512 specification; using an unsupported immediate value MAY result in undefined behavior.