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VP4DPWSSDS

This instruction performs a packed double-precision floating-point subtract with a double-precision saturation, processing elements in a vectorized manner. It subtracts the second operand from the first, and the result is saturated to the maximum or minimum representable double-precision floating-point value if the result overflows.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is ONLY available in 64-bit mode or compatibility mode. It REQUIRES support for AVX-512 and the specific foundation or extension subset that implements the VP4DPWSSDS opcode.

The instruction's behavior is governed by the MXCSR register settings. Specifically, the rounding mode defined in MXCSR SHALL be applied to the subtraction operation. If the result exceeds the representable range of a double-precision float, it SHALL be saturated rather than resulting in $\pm\infty$, provided the specific saturation flags are active. Failure to ensure the correct AVX-512 feature set is enabled in the CPU will result in an invalid opcode exception.