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VMOVW

Moves a packed word value from the source to the destination.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available in 64-bit mode and compatibility mode. It requires the SSE2 instruction set extension.

The instruction operates on the lowest 16 bits of the XMM registers. The upper bits of the destination register remain unchanged. When using a memory operand, the memory access SHALL be aligned to a 2-byte boundary to avoid performance penalties, although unaligned access is supported.