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VMINPH

Computes the minimum of two packed half-precision (16-bit) floating-point values. The instruction compares the values and returns the smaller of the two. If one of the operands is a NaN, the result is the other operand; if both are NaN, the result is a NaN.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction SHALL be used only in 64-bit mode or compatibility mode. It REQUIRES the AVX-512 F floating-point extensions (AVX-512 FP16) to be supported by the processor.

When using the evaporated form of the instruction (without masking), the destination register SHALL be overwritten. When using the masked version, the merge-masking behavior ensures that only the elements corresponding to the set bits in the mask register are updated in the destination; other elements SHALL remain unchanged. To avoid unexpected behavior, ensure the mask register is correctly initialized, as uninitialized mask bits may lead to inconsistent data in the destination register.