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VFNMSUB132SS

Subtracts the second operand from the first operand, negates the result, and stores the result in the destination. This instruction operates on the lowest 32 bits of the scalar floating-point operands.

The table below covers what the source and destinations can be.

DO NOT support LOCK

This instruction requires the AVX instruction set to be supported by the processor. It is available in 64-bit mode and compatibility mode.

The destination register is overwritten by the result; therefore, it cannot be used as a read-only source if the original value must be preserved. When using the three-operand form, the destination is independent of the sources.

The operation is subject to x87-style floating-point exception flags. Specifically, it may trigger #P if the result is inexact, or #O if the result exceeds the maximum representable value for a 32-bit float. Denormal operands may trigger #D depending on the MXCSR register settings (Flush-to-Zero or Denormals-Are-Zero).