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VFNMSUB132SD

Subtracts the product of two floating-point values from a third floating-point value and stores the result in a destination. Specifically, it computes $dest = -(a \times b) + c$, where $a$ and $b$ are scalar double-precision floating-point values and $c$ is a scalar double-precision floating-point value.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires the AVX instruction set to be supported and enabled by the processor.

The instruction utilizes the YMM registers but operates only on the lower 64 bits (the scalar double-precision portion). The upper bits of the YMM destination register are preserved. Ensure that the processor state allows AVX execution to avoid #UD (Undefined Instruction) exceptions. Floating-point exceptions #D, #Z, #O, #U, and #P may be raised depending on the result and the MXCSR register settings.