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VFNMSUB132PS

Subtracts the product of the second source operand and the third source operand from the first source operand, then negates the result. The operation is performed on packed single-precision floating-point values.

The following table specifies the supported source and destination operands.

DO NOT support LOCK

This instruction is only available in 64-bit mode or 32-bit mode. It REQUIRES the AVX CPU feature flag to be enabled.

The operation is subject to the floating-point control word settings. Results may trigger floating-point exceptions including #D, #O, #U, and #P depending on the rounding mode and the magnitude of the operands. Since this is a fused multiply-subtract operation, it performs the multiplication and subtraction with a single rounding step at the end, which minimizes precision loss compared to discrete instructions.