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VFNMSUB132PH

Subtracts the product of two floating-point half-precision (f16) values from a third floating-point half-precision value, then negates the result. The operation is performed as: $dest = -(src1 - (src2 \times src3))$.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction requires AVX-512 FP16 support. It is only available when the processor is operating in 64-bit mode.

The operation follows the IEEE 754 standard for half-precision floating-point arithmetic. Precision and rounding are controlled by the MXCSR register. If the result is too large to be represented in f16 format, it results in #O. If the result is too small, it results in #U. Any inexact result triggers #P. Denormalized operands may trigger #D depending on the flush-to-zero (FTZ) and denormals-are-zero (DAZ) flags in MXCSR.