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VFNMSUB132PD

Subtracts a floating-point value from the product of two floating-point values, then negates the result. Specifically, it computes the result as: $-(a \times b) + c$.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction is available only in 64-bit mode or compatibility mode. It requires a processor supporting the AVX512 foundation.

The instruction uses the destination register as the addend ($c$), and the two source operands as the multipliers ($a$ and $b$). If the destination register is also used as one of the source operands, the original value is overwritten by the result.

The operation is subject to floating-point exceptions: #O, #U, #P, and #D. If the input values are signaling NaNs, #I shall be raised. The rounding mode is governed by the MXCSR register.