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VFNMADD231SD

Performs a fused multiply-subtract operation on scalar double-precision floating-point values. It computes the result as $dest = (src1 \times src2) - src3$ and stores it in the destination.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction requires the AVX support bit to be enabled in the CR4 register; otherwise, it SHALL trigger an #UD exception. It operates exclusively in 64-bit mode or compatibility mode when using YMM registers.

The instruction is subject to the floating-point control word settings in the MXCSR register. Specifically, rounding mode and exception masking SHALL affect the final result. Inexact results SHALL trigger #P, and overflows SHALL trigger #O according to the current rounding mode. To avoid performance degradation due to "denormal-as-zero" or "flush-to-zero" behaviors, ensure the MXCSR register is configured to handle denormalized operands (#D) consistently.