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VFNMADD231PD

Computes a fused multiply-add operation for double-precision floating-point values. It calculates the result as: destination = -(a * b) + c, where the operands are mapped according to the 231 pattern (source1 * source2) is subtracted from source3.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction SHALL only be executed in 64-bit mode or 32-bit mode. It REQUIRES the AVX-512 foundation extensions. The instruction is not supported in compatibility mode.

The instruction is subject to floating-point exception flags. Results MAY trigger #P, #O, #U, or #D based on the MXCSR register settings. If the result is a NaN, the specific NaN type depends on the operands. To avoid precision loss or unexpected rounding, the user MUST ensure the rounding control field in MXCSR is correctly configured, as FMA operations perform a single rounding step at the end of the combined multiply-add sequence.