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VFMSUBADD231PH

Performs a fused multiply-subtract and add operation on packed half-precision floating-point values. For each corresponding element of the input vectors, the instruction computes $(a \times b) - c + d$ and stores the result in the destination.

The following table specifies the supported source and destination types.

DO NOT support LOCK

This instruction is only available when the processor is operating in 64-bit mode or compatibility mode and requires AVX-512 support.

The operation is performed using the precision and rounding mode specified in the MXCSR register. The result is subject to standard IEEE 754 floating-point exceptions, including #D, #O, #U, and #P. If the operation results in an overflow, #O is signaled.