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VFMSUBADD231PD

Performs a fused multiply-subtract and add operation on double-precision floating-point values. It computes the result of (a * b) - c + d for the first element of the vector and (a * b) + c - d for the second element, where a, b, c, and d are the input operands.

The following table covers the supported source and destination operands.

DO NOT support LOCK

This instruction is available only when the AVX-512 foundation instructions are supported. It requires the processor to be in 64-bit mode or compatibility mode.

The operation is performed with a single rounding step at the end, which prevents the loss of precision associated with intermediate rounding. Users SHOULD ensure that the processor supports the AVX-512F feature set to avoid #UD (Undefined Instruction) exceptions.

The instruction may trigger the following floating-point exceptions:

• #O: If the result exceeds the maximum representable value.
• #U: If the result is smaller than the minimum representable value.
• #P: If the result is not exactly representable.
• #D: If a denormalized operand is encountered.