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VFMSUB231PS

Performs a fused multiply-subtract operation on packed single-precision floating-point values. The operation computes the result of $(a \times c) - b$ for each corresponding element of the input vectors, where $a$ is the first source operand, $b$ is the second source operand, and $c$ is the third source operand.

The following table describes the supported source and destination operands.

DO NOT support LOCK

This instruction is only available when the processor supports the AVX-512 foundation instructions. It requires the processor to be operating in 64-bit mode or compatibility mode.

The operation is performed as a single floating-point step with one final rounding, which prevents the loss of precision that occurs when performing a multiply followed by a separate subtract. If the destination register is also used as a source, the original values are overwritten. Users SHALL ensure that the appropriate AVX-512 feature flags are checked via CPUID before execution to avoid invalid opcode exceptions.

The result of the operation may trigger floating-point exceptions: #D if a denormalized operand is encountered, #O if the result overflows, #U if the result underflows, and #P if the result is inexact.