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VFMSUB231PD

Computes the fused multiply-subtract of two double-precision floating-point values and subtracts the result from a third double-precision floating-point value. The operation is performed as: $\text{destination} = \text{source1} - (\text{source2} \times \text{source3})$.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction requires AVX support. It is not available in compatibility mode; it requires 64-bit mode or 32-bit mode with AVX enabled.

The destination register must not overlap with any of the source registers to avoid undefined behavior. This instruction utilizes the MXCSR register for rounding control and exception masking.

The instruction will trigger floating-point exceptions such as #O, #U, #P, or #D based on the result of the fused operation and the state of the MXCSR register. Because it is a fused operation, only one rounding step is performed at the end, which prevents intermediate precision loss.