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VFMSUB213SH

Performs a fused multiply-subtract operation on signed short floating-point values. It computes the result of $(a \times b) - c$ using the provided operands, where the result is stored in the destination.

The following table specifies the supported source and destination operands.

DO NOT support LOCK

This instruction is available only when the processor supports the AVX-512 Foundation and the AVX-512 FP16 extensions. It SHALL only be executed in 64-bit mode or compatibility mode.

The operation is performed on the lower 16 bits of the elements within the zmm/ymm/xmm registers. If the destination register is also used as a source for the subtrahend ($c$), the original value SHALL be preserved until the final subtraction occurs. Precision and rounding are governed by the MXCSR register.

To avoid precision loss or unexpected exceptions, ensure that the MXCSR rounding mode is correctly configured. Operations may trigger #P, #O, #U, or #D depending on the input magnitudes and the resulting value's proximity to the representable range of f16.