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VFMSUB132SH

Performs a fused multiply-subtract operation on signed packed 16-bit floating-point values. The instruction computes the result of $dest = (a \times b) - c$, where $a$ and $b$ are the first two source operands and $c$ is the third source operand, and stores the result in the destination.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction SHALL only be executed when the processor is operating in 64-bit mode or compatibility mode. It REQUIRES AVX-512 foundation and the specific AVX-512 FP16 extension support.

The destination register is SHALL be one of the first two source operands. If the destination register is not one of the sources, the operation is #I. Precision and rounding are governed by the MXCSR register; failure to set the correct rounding mode may result in #P.