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VFMSUB132SD

Performs a fused multiply-subtract operation on scalar double-precision floating-point values. The instruction computes the result of $a \times b - c$ and stores it in the destination, where $a$ is the first source operand, $b$ is the second source operand, and $c$ is the third source operand.

The following table describes the supported source and destination operands:

DO NOT support LOCK

This instruction is only available when the processor supports the AVX-512 foundation. It requires the execution environment to be in 64-bit mode or a compatibility mode that supports AVX-512 instructions.

The operation is performed as a single fused step with only one rounding stage at the end, which prevents intermediate precision loss and avoids the #P exception that would occur if a separate multiply and subtract were used. If any operand is a signaling NaN, a #S exception may be raised. The result is subject to standard IEEE 754 rounding modes as defined in the MXCSR register.