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VFMADDSUB231PH

This instruction performs a fused multiply-add or multiply-subtract operation on packed half-precision floating-point values. It computes the result as $res = (a \times b) + c$ or $res = (a \times b) - c$ depending on the immediate operand, where $a$ and $b$ are the source operands and $c$ is the accumulator.

The following table specifies the valid source and destination operands.

DO NOT support LOCK

This instruction is only available in 64-bit mode and 32-bit mode. It REQUIRES the AVX-512 FP16 extension to be enabled. The instruction operates on zmm or ymm registers; using it in compatibility mode without proper AVX-512 support will result in an invalid opcode exception.

The operation is performed according to the IEEE 754-2008 standard for fused multiply-add. Only one rounding operation is performed at the end of the computation, which prevents intermediate rounding errors. Precision exceptions #P and underflow #U may be triggered based on the MXCSR register settings. If the result exceeds the representable range of f16, a numeric overflow #O occurs. Denormalized inputs are handled according to the flush-to-zero (FTZ) and denormals-are-zero (DAZ) flags in MXCSR; otherwise, they may trigger #D.