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VFMADDSUB132PD

Performs a fused multiply-add or multiply-subtract operation on packed double-precision floating-point values. Depending on the immediate operand, it computes either $r64a = (r64a \times r64b) + r64c$ or $r64a = (r64a \times r64b) - r64c$. The "132" notation indicates that the first operand is multiplied by the second, and the result is added to or subtracted from the third.

The following table covers what the source and destinations can be.

DO NOT support LOCK

This instruction SHALL be executed in 64-bit mode or 32-bit mode; it is NOT available in compatibility mode if the processor does not support the corresponding AVX/AVX2/AVX-512 extensions. The instruction requires the YMM or ZMM registers; if used with XMM registers, it operates as a subset of the AVX-512 foundation.

The instruction SHALL trigger floating-point exceptions including #P, #O, #U, #D, and #Z based on the result of the fused operation. Because it is a fused operation, only one rounding step is performed at the end, which prevents intermediate precision loss. Users MUST ensure that the appropriate AVX or AVX-512 CPUID flags are checked before execution to avoid #UD (Undefined Instruction) exceptions. When using ZMM registers, the upper bits of the destination register are zeroed if the operand size is smaller than the register size (masking behavior applies in EVEX encoded versions).