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VFMADD231SH

Computes the product of two floating-point operands and adds the result to a third floating-point operand, then stores the result in the destination. Specifically, it performs the operation: $dest = (src1 \times src2) + src3$, where the operands are formatted as $f16$ (half-precision).

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction is only available in 64-bit mode. It requires the AVX-512 FP16 extension.

The operation is performed using the precision and rounding mode specified in the MXCSR register. If the operation results in a value that cannot be represented as an $f16$, the instruction may trigger #O or #U exceptions. The result is subject to #P if the result is not exact. If any operand is a signaling NaN, it SHALL trigger #I.