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VFMADD231PH

Multiplies a packed set of half-precision floating-point values (f16) from the first source operand by a packed set of half-precision floating-point values from the second source operand, adds the result to a packed set of half-precision floating-point values from the third source operand, and stores the result in the destination operand. The operation follows the form: dest = (src1 * src2) + src3.

The following table covers the supported source and destination operands.

DO NOT support LOCK

This instruction SHALL only be executed in 64-bit mode or 32-bit mode. It requires the AVX-512 Fused Multiply-Add (FMA) and AVX-512 FP16 extensions to be enabled in the processor.

To avoid precision loss or unexpected behavior, the user SHALL ensure that the floating-point control word is correctly configured. The instruction produces results based on the current rounding mode. Failure to handle floating-point exceptions may result in #I, #Z, #D, #O, #U, or #P being set in the MXCSR register. Use of this instruction on non-aligned memory operands may result in a general-protection exception if alignment checks are enabled.