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VFMADD132SD

Performs a fused multiply-add operation on scalar double-precision floating-point values. It computes the result of f64(a * b + c) where the operands are provided in the order specified by the 132 permutation (third operand, first operand, second operand), and stores the result in the destination.

The following table covers what the source and destinations can be:

DO NOT support LOCK

This instruction SHALL be executed in 64-bit mode or 32-bit mode. It is NOT available in compatibility mode. The instruction requires the FMA3 extension to be supported by the processor.

The operation is performed as a single ternary operation with unbounded precision before rounding, which avoids intermediate rounding errors. The instruction MAY trigger the following floating-point exceptions: #I, #D, #O, #U, and #P. If any operand is a Signaling NaN, #I is signaled. The behavior of the rounding is governed by the rounding control bits in the MXCSR register.