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VFCMULCPH

Multiplies two packed half-precision floating-point numbers and rounds the result to the nearest half-precision floating-point number using the rounding mode specified in the immediate operand.

The following table covers the supported source and destination operands.

DO NOT support LOCK

This instruction is only available in 64-bit mode or compatibility mode. It requires the AVX-512 FP16 extension.

The rounding mode is controlled by the 3-bit immediate operand; if the immediate is not provided, the rounding is governed by the MXCSR register. The result is subject to the following floating-point exceptions: #I, #D, #O, #U, and #P.

Failure to ensure the processor supports the AVX-512 FP16 feature flag before execution WILL result in an #UD (Undefined Instruction) exception. The alignment of memory operands MUST be consistent with the vector size to avoid general protection faults or performance penalties.