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VERW

Writes a dword to the destination operand and reads a dword from the source operand. In 64-bit mode, this instruction is frequently used to execute a serialization operation to flush cached memory translation entries, specifically to clear the write-combining buffers.

The table after the description covers what the source and destinations can be.

DO NOT support LOCK

The instruction MUST be used with memory operands. Using registers or immediates SHALL result in an invalid operation.

In 64-bit mode, VERW is specifically utilized as a mechanism to flush internal processor buffers. When the destination operand is a memory location, the processor ensures that previous stores are completed before the write occurs. This is critical for avoiding data corruption or synchronization issues when interacting with memory-mapped I/O or during specific power-management transitions.

The operand size MUST be dword. Using different operand sizes SHALL lead to unpredictable behavior or failure to trigger the intended buffer flush. To avoid issues when attempting to clear write-combining buffers, ensure the memory operand points to a valid, writable memory location.